Group: 2014-FYP-22



Dr. Ubaid Ullah Fiaz


Polar codes are mathematically proven to achieve Shanon capacity. Due to a sufficiently high channel achieving capacity and polar codes is believed to surpass turbo codes in communication technology. The encoding and decoding algorithms have been developed to work on MATLAB or on a microcontroller processor. But it gives very low throughput which was a significant constraint for its effective implementation. So we have designed Encoder and Decoder Cores on register-transfer level (RTL) and tested on Field Programmable Gate Array (FPGA) device. The state-of-the-art soft-output decoder for polar codes is a message-passing algorithm based on Belief Propagation (BP), which performs well at the cost of high processing and storage requirements. We propose a low-complexity alternative for soft-output decoding of polar codes that offers better performance but with significantly reduced processing and storage requirements. We have designed a high throughput encoder for polar codes with parameterized input data. The design maintains maximum throughput with low hardware complexity by employing both combinational and sequential logic cleverly. A polar code encoder was implemented since the input to the encoder at the sending end should match the output of the decoder at the receiving end. This encoder has been used to test the decode also. We have designed parameterized encoder for 2 n input bits, where n is greater or equal than 2 while less than or equalthan 15. Thus this encoder works for 4 to 32,768 bits input. Similarly, the hardware for the decoder was designed utilizing as minimum resources as possible. This decoder is parameterized for any number of iterations without addition of any hardware complexity. The design of cores was first simulated on ModelSim and then tested on Xilinx Spartan-3 FPGA. Glue logic was developed to test the cores which provide interface between our cores and computer by employing Universal Asynchronous Receiver Transmitter (UART). Thus we compared the data from our cores with existing algorithm output in MATLAB by getting data out of FPGA. We have tested our cores for at least 50,000 random cases.

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